Zeroplus Logic Cube LAP-C 16032 Logic Analyzer LAP-16032U
Product Description
In Stock16-channel 100MHz Logic Analyzer with 4 built-in protocol analyzer.
Special introductory offer: 2 free additional protocols from the following list:
- 1-wire
- HDQ
- CAN 2.0B
- SIGNIA 6210
- USB 1.1
- IIS
- PS/2
- Microwire
- SSI
- S/PDIF
- LIN 2.1
- Manchester
- Miller
- IRDA
- SD2.0/SDIO (Unsupported at full speed on LAP-C 16032 and 16064 models)
- LPC-SERIRQ (Unsupported on LAP-C 16032 and 16064 models)
- LPC (Unsupported on LAP-C 16032 and 16064 models)
- DIGRF (Unsupported on LAP-C 16032 and 16064 models)
- LCD1602
- ST
- JTAG 2.0
- ST7669
- MOD
- FLEXRAY 2.1A
- DMX512
- CCIR656
- PCM
- DSA
- NEC PD6122
- MII
- LCD 12864
- PM 1.1
- SM 2.0
- PSB
- SLE4442
- AC97
- 3-Wire
- PECI
- i2c (Serial EEPROM 24L Series)
- ISO7816 UART
- Modified Miller
- SDQ
- HAD
- UNI/O
- Modified SPI
- Wiegand
- SPI Plus
How to get the free protocols: Once you purchase and receive the Logic Cube 16032U logic analyzer, you need to install the software and then connect the logic analyzer to the PC or Laptop. The software will show the serial number of the device. email the serial number with the 2 protocols of your choice to zeroplus@nkcelectronics.com. We send the passcode request to Zeroplus. In the meantime, you can download the protocol plug-in installable executables from www.zeroplus.com.tw --> technical support --> downloads. Once we receive the passcodes from Zeroplus, we will email them to you. You activate the protocols using the passcodes.
Hardware Specifications
| Interface | USB 2.0 (1.1) |
| Operating System | 98SE/ME/2000/XP/VISTA |
| Power Supply | USB 1.1 (USB 2.0 Recommended) |
| Channels | 16 |
| Bandwidth | 75MHz |
| Memory Depth (Per Channel) | 32Kbits |
| Memory | 512Kbits |
| Internal Clock Rate (async) | 100Hz - 100MHz |
| Max External Clock (sync) | 75MHz |
| Trigger Channels | 16 Channels |
| Trigger Condition | Edge/Pattern |
| Pre-Trigger/Post-Trigger | Yes |
| Trigger Level | 1 Level |
| Trigger Count | 1-65535 |
| Max Trigger Page | Max 8191 |
| Filter Channel | 16 |
| Buses Data Decoded | Yes |
| Enable Delay | Start: Edge and Pattern. End1-65535 |
| Compression | 16 Channel Compression 1-255 |
Electrical Specifications
| Minimum | Typical | Maximum | |
| Working Voltage | DC 4.5V | DC 5.0V | DC 5.5V |
| Current at Rest | 200 mA | ||
| Current at Work | 400 mA | ||
| Power at Rest | 1 W | ||
| Power at Work | 2 W | ||
| Error in Phase Off | +/- 1.5 ns | ||
| Vinput of Testing Channels | +/- DC 30V | ||
| VReference | DC -6V | DC +6V | |
| Input Resistance | 500Kohm/10pF | ||
| Working Temperature | 5 C | 70 C | |
| Storage Temperature | -40 C | 80 C |
Package Contents
| Logic Analyzer | 1 |
| 16-pin Testing Cable | 0 |
| 8-pin Testing Cable | 2 |
| Probe | 2 |
| USB Cable | 1 |
| Getting Started Guide | 0 |
| Driver CD & Software | 1 |
| 1-pin Testing Cable (hite) | 1 |
| 2-pin Testing Cable (Black) | 1 |
| Built-In Protocols (Free) | SPI, IIC, 7-segment, UART |
| Optional Protocol add-ons | 1-wire, HDQ, CAN 2.0B, SIGNIA 6210, USB 1.1, IIS, PS/2, Microwire, SSI, S/PDIF, LIN 2.1, Manchester, Miller, LCD1602, ST, IRDA, JTAG 2.0, ST7669, MOD, FLEXRAY 2.1A, DMX512, CCIR656, PCM, DSA, NEC PD6122, MII, Digital Logic, Arithmetic Logic, LCD 12864, PM 1.1, SM 2.0, PSB, SLE4442, AC97, 3-Wire, JK Flip-Flop, PECI, UpDownCounter, i2c (Serial EEPROM 24L Series) |
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